Skip to content
binho.io (opens in a new tab)Contact Us

I2C, which stands for Inter-Integrated Circuit, is a de-facto standard protocol for inter-chip communication widely used for attaching lower-speed peripheral ICs to processors and MCU in short-distance, intra-board communication.

With a similar approach as SPI, Binho Mission Control presents a streamlined yet potent interface to operate the I2C protocol. The Command Panel is divided into three segments: settings, selection of target devices by address, and execution of I2C transactions.

I2C command panel for Supernova and Pulsar.

Settings segment for Nova.

The Settings segment allows users to adjust the following parameters:

ParameterNova valuesSupernova valuesPulsar valuesComment
Clock Frequency100 kHz to 3.4 MHz100 kHz to 1 MHz100 kHz to 1 MHz4 values available if Non-Standard Frequencies switch is off (for Nova).
Internal Pull-Up ResistorsOn/Off150 Ω to 10 kΩ150 Ω to 4 kΩNova pull-up resistor value is fixed.
Bus Voltage3.3 V1.2 V to 3.3 V1.2 V to 3.3 VIn Supernova and Pulsar, users can measure voltage and select an external power source.

Notes:

  • Clock Frequency: The Binho Nova and Binho Supernova facilitate I2C bus clock frequencies ranging from 100 kHz to 3.4 MHz, covering all typical operating modes. Enabling the “Non-Standard Frequencies” option lets users input any desired clock frequency within this range.
  • Open Drain Configuration: I2C’s electronic-level execution employs an open-drain configuration, necessitating at least one pull-up resistor for the SDA and SCL pins. The app allows users to activate the in-built pull-up resistors in the Binho Nova.
  • I2C Buses: Binho Pulsar exposes two independent I2C buses (I2C_BUS_A and I2C_BUS_B), while Binho Supernova exposes one (I2C_BUS_A).

Click the “Address” textbox and the host adapter scans for connected devices and lists them for selection. An address can also be typed in hexadecimal.

Target Device segment for Nova

Featured parameters and allowed values:

ParameterAdmited valuesComment
AddressHexadecimalByte grouped.
Address format7-bit, 8-bit.
SubaddressHexadecimalOptional.

Notes:

  • Address Formats: Both 7-bit and 8-bit address lengths are accommodated. The former uses its initial bit to discern between read and write operations, while the latter assigns distinct addresses for both procedures.
  • Subaddress: This optional parameter can pinpoint a specific device register or a memory cell.

Transactions segment

This segment is dedicated to I2C read/write transfers:

  1. Write Buffer: Users enter the data payload meant for the target device here, in hexadecimal format grouped by byte packets. The WRITE button confirms the transaction.
  2. Read Size: Specifies the byte amount to be retrieved from the target device. Initiating a read operation is as simple as pressing the READ button.

The Onsemi CAT24C512 is an I2C EEPROM 512 kb memory that supports Standard, Fast, and Fast-Plus modes. To our knowledge, it lacks pull-up resistors for its SCL and SDA pins, so we activate them via the I2C command panel. We also select a clock frequency of 400 kHz (Fast mode).

When we place the cursor within the “Address” input box, the app automatically detects the memory at address 0x50. We write the payload 0xDE.AD.BE.EF to the subaddress 0xAB.CD. Subsequently, altering the subaddress to 0xAB.CB and requesting an 8-byte read yields the result 0xFF.FF.DE.AD.BE.EF.FF.FF, precisely what we anticipated based on the datasheet’s default register values.

Write and Read transactions performed with an EEPROM memory.