Binho Atira: Troubleshooting
Fixes for a Binho Atira that is not found, will not attach to the target or gives no UART data, and the probe’s known limitations.
The probe is not found
Section titled “The probe is not found”| Observed | Meaning |
|---|---|
An empty list from list_debug_probes() | The probe is not on USB. Try another cable or port. |
DeviceNotFoundError | Another program holds the probe (only one program can own it), or on Linux the udev rule is missing. See Linux: udev rule. |
UnsupportedFirmwareError | The probe runs firmware older than 1.0. See Firmware. |
SWD will not attach
Section titled “SWD will not attach”- Check that the target rail is on and reads about 3.3 V. With the rail off, SWD cannot connect.
- Check that the cable is straight, not mirrored: pin 1 to pin 1 at both ends.
- If the target board has its own on-board debugger (ST-LINK, MCU-Link), hold it in reset or unpower it so it does not drive SWDIO and SWCLK. On a NUCLEO-H503RB, fit JP1.
- Do not wire the target’s own supply to J4 pin 1 while the rail is on: that puts two supplies in parallel. See Target power.
SPI flash does not respond
Section titled “SPI flash does not respond”- Switch the target rail on first: it powers the flash on J4 pin 1.
- Wire the flash as in J4 as an SPI flash header, with /WP and /HOLD tied to VCC.
- Disconnect any SWD target from J4. SPI uses pin 9 as chip select, and some debug targets tie it to ground.
- Keep the clock at 8 MHz or lower.
The UART bridge gives no data
Section titled “The UART bridge gives no data”- Switch the target rail on first: the level shifters on J2, J3 and J4 run from it.
- Ask the SDK which serial port belongs to the probe: UART bridge port.
- Check that TX and RX are crossed (probe TX to the target’s RX), and that J2 pin 3 is not wired to a target pin: it carries 3.3 V.
pyOCD reads wrong data
Section titled “pyOCD reads wrong data”A flash read taken while the target runs can return wrong data (mostly zeros on the STM32H503). Halt the core first. See Flashing a target MCU with pyOCD.
Known limitations
Section titled “Known limitations”- SPI clock tops out at 8 MHz. The firmware refuses a higher clock.
- SWD, SPI and UART need the target rail on, because the level shifters run from it. This applies to self-powered targets too (leave J4 pin 1 unconnected).
- JTAG after SWD: an SWD session puts the target’s JTAG TAP to sleep until the target power-cycles; a reset alone does not wake it. Relevant only to mixed SWD/JTAG setups with other tools.
- Windows: SPI flash programming uses the slower HID path. pyOCD flashing has been verified on Linux only.
- No RTT, SWO, UPDI or JTAG in Atira firmware 1.0 (see Not yet available).
Still stuck? Email [email protected] with the probe’s serial number, its firmware version and the action being attempted.